System for reconfiguring central processor and instruction storage combinations

ABSTRACT

A system is disclosed including duplicate copies of central processors and storage means for switching active copies of central processor and primary copies of instruction through all combinations to find a working combination. The reconfiguration may be effected either through a fixed wired recovery control circuit which changes state in predetermined sequence or, alternatively, under program control.

United States Patent 1191 Wilber et a1. 5] Aug. 6, 1974 [54] SYSTEM FOR RECONFIGURING CENTRAL 3,409,877 11/1968 Alterman et al 340/1725 mCESSOR INSTRUCT'ON 5223312 31133? ??2""';;;i 2381535? 011 me t r ,1 STORAGE COMBINATIONS 3,623,014 11/1971 Doelz et al 340/1725 [75] Inventors: John A. Wilber, Elk Grove Village; 3,641,505 2/1972 Artz v. 340/1725 verner K. Rice whgaton; Rolfe E. 3,654,603 Gunning Cl 81. 340/1715 X Buhrke, La Grange Park, all of Ill.

{73] Assignee: GTE Automatic Electric Primary Examiner-Harvey E. Springborn Laboratories Incorporated, Northlake, Ill. 22 Filed: Mar. 15, 1973 [57] ABSTRACT [2]] Appl. No.: 341,428 A system is disclosed including duplicate copies of central processors and storage means for switching active copies of central processor and primary copies of [52] 'i g 315 instruction through all combinations to find a working [51] G m combination. The reconfiguration may be effected ei [58] 0 arc 3 I ther through a fixed wired recovery control circuit which changes state in predetermined sequence or, al- [56] UNITE D ;$?ES S:FENTS ternatively, under program control.

3,386,082 5/1968 Stafford et a1. 340/1725 11 Claims, 51 Drawing Figures ACCESS TRUNK! Pram/rm. car/mourn MATRIX DECODE a c DATA ms E5 1 0 cmcurT EGISTER INS TRU CTION STORE TO OTHER URI 5 CENTRAL PROCESSOR nccrss CIRCUIT NPUT- OUTPUT CIRCUIT PROCESSOR CONTROL C I RCU/T TO OTHER PS UM T5 PATENTH) Mill 5 7374 FIG.3

SHEEI 0% 0f 23 TIMING GENERA TOR CIRCUIT 6P4) 50 5O CPI ma 1 T66 LEVEL LEVEL ,52 MC "ENERATDR sEMRAr MAC 666 cm. I SWITCH/N6 "smrcnma cnns ccc SSBYL r X CONTROL ssan. mc MCC .Iswrrcmwa smmnma ncc PMC NETWORK NETWORK pm L51 5/ 1| Rcc rmma mum Rcc rmE LEVELS LEVELS TIME r0 6P0 T0 4 H6 4 he nooEpaAm READ/WRITE g; MEMORY AND LEVELS '00 [SR PERIPHERAL MAC ICC INSTMTION UNI];

cow 0L CIRCUITS 55 DP 6 CMPALCIPU AND 0pc DECODING Mm E INEXFRL CIRCUITS MMC 10c REGISTER 53 AND PLACE ACCEPT A no LEVELS ACCEPT DPC I CONTROL CIRCUITS us RANSFER aus .LEVELS TRANSFER com'RoL 0M cmcu/rs V 55 PROCESSOR CONTROL CIRCUIT (FCC) PATENTED 3.828.321

saw near 23 CPQ FIG. II cm I RCC a RC6 is CH Q M46 M66 1 I MCC MAC I I I I I, CONFIGURATION I I counaurmnow corvmoL cozvmoz. CIRCUIT I cmcu/r I CPAL I I cPAL I00 I I c cPAL (BUS I mus CONFIGURATION) CONFIGURATION) II TLGC MMC [cc I use MMC [60 f5? fix CONFIGURATION con/mm cmcu/r FIG. I2 MA'sB Q1 100 I :00 0 c 0P6 oPc 0P6 P cc I I Pcc TGC CCC IMRB I I MR3 IMDB I IM 08 uvsa I ms I rec PCC rec P00 060 I00 ccc 100 R66 rcc ncc rcc me we I ma mwc MAINTENANCE ACCESS CIRCUIT PATENTED 3.828.321

SHEEI 10 Q? 23 FIG [5 TIM/N6 GENERATOR PULSE CHART 0 l0 0 REcOIvEIOuRArIOIv CYCLE 0 r! 2 .0 4O 5. 6.0 Z0 8.0 90 IO .5 I5 2 .5 I05 #20 l I 1 15 l 1 1 415 F 1 I 1 l I 1 l I START OF TIMING GENERATOR 5001/ sEc, Rrz JLusEO T0 GENERATE CPTL, SICBL, RICCL, MIALL AND MAALL O .5 SEC I40 SEC RT2L| I USED TO GENERATE CPSWL 0 l0 1! SEC.

IOOsEc. RrsL I usEO r0 GENERATE RcEL 50011 SEC. RT4L2 n usEO r0 GENERATE ASE'L AND ASOL NOTE) RCC LOCKED OUT TO TRIGGERS FROM START OF CYCLE UNTIL END OF CYCLE (2) RT4L CAN OCCUR ANY TIME AFTER RT3L AND RT5L, NEW

RCC STATE STARTS AT END OF RT4L E5621 NEXT E z; C g smrE I'RAIvsITIOII TABLE ROEQROPSI EEEQQMEGEZZQ FUNCT'ON PRIME Rcc FOR CP SWITCH III CASE 5 P X 5 I X X X X REcOvERY PROGRAM INDICATES AOr/vE OP MALFUNCT/ON 5O X 5/ XXX X X 57,497 5gp SWITCH cP's IF STANDBY Is NOT X 52 X X X X III TROUBLE,- sTARr sRP I51 BECOMES PRIMARY INSTRUCTION 52 X 53 X X X X X TQRE smRr sRP EORcE CP SWITCH; Isc REcOIIIEs 53 X 52 X X X X X X X X PRIMARY/NSTRUCT/ON STORE srART sRP MAIN rEIvcE OOIWROL GROUP 9 000/0203 MCG-8 31 F1619 R H R R c c c c s s s r R c c O F F O R R s Rcc coIvrRoL POINTS MAINTENCE sEIvsE GROUP 8 00 00203 use-s 31 R 5 g 0 FIG 20 8 c A a s F F F F PATENTEDAUG 61w 3.828.321

sum NW 23 FIG 2 2 5 T D T OUTPUT szr com/1110s szr/ RESET RESET comm/1110s -D DUAL RANK FLIP FLOP IMPLEMTATION FIG. 23

INST FETCH DATA FETCH g gi ALT-UP sa CP ACTCP 50/ CP 0 a r 0 55m) 11105510011: swam: $1110 1110 Is CONFIGURATION 0 0 0 0 0 1 1 0 0 1 1 DUPLEX 0 0 0/10/1 0/1 0/1 on 0/1 M69650 0 0 0 0 1 1 1 SIMPLEX-DIAGNOSTIC 0 0/1 0 0 0/1 0 0 .SIMPLEX-UPDATE 0 0/1 0 0 1/0 1 1 SIMPLH-UPDATE-DIAG.

1 1 1 0 0 1 1 0 0 DUPLEX [/0 I/O I/O /0 I/O I/O MEG-ED I I I I I I I SIMPL EX I I I I 0 0 0 SIMPLE X-DIA GHOST/C l/O I I I/O I I SIMPLEX-UPDATE I/O I I 0/ I O O SIMPLEX-UPDA TE-DIA G Is BUS CONTROLS MID Rzsuuma counaunnnous PATENTED RUB 5 974 SHEET 1 0f 23 FIG: 24

IS BUS CONTROL LEVEL EQUATIONS DEFINITION OF TERMS:

U-CWO DCPAL DCCAF s|sBL SISBIL RISBL RISBIL xEc XECN

SISB L RISBOL SISBIL RISBH.

ISCBF BUS cONTROL FLIP-FLOP OUTPUT ISBBF BUS CONTROL FLIP-FLOP OUTPUT ISTBF BUS cONTROL FLIP-FLOP OUTPUT ISDBF BUS CONTROL FLIP-FLOP OUTPUT DIAGNOST|C CP ACTIViTY LEVEL (DCPAL CPAL v DF) DUAL CYCLE CONTROL A FLIP-FLOP (INPUT LEVEL FROM FCC) sENO |s* BUS O LEVEL SEND 1s* BUS 1 LEVEL RECEIVE |s* BUS O LEVEL RECEIVE 15* BUS 1 LEVEL EXECUTE INSTRUCTION ExEcuTE NON MEMORY INSTRUCTION PATENTEB AUG 51974 SHEET 17 8f 23 kmqoibu SEE Q 1 xQQQ hm mt 312G mH mam Q mam L mam mm x QQEEM MMGI as New 

1. A programmable data processing system having first and second central data processors each including processing circuits and maintenance circuits, and first and second storage means, one of said storage means being adapted respectively to be connected in signal communication with one of said central processors and the other storage means being adapted to be connected in signal communication with the other central data processor under normal operating conditions, said maintenance circuits sensing conditions within said system to generate error signals upon detection of faults, said system further including a system recovery program, wherein the improvement comprises: subsystem circuit means in each data processor for connecting said first and second central processors with said first and second storage means to form predetermined configurations thereof, one of said central processors being active and the other being passive at any one time, said subsystem comprising recovery control circuit means including state control circuit means for generating state signals representative of a plurality of predetermined states, and control logic circuit means responsive to said error signals to actuate said state control circuit to generate said state signals in predetermined order as defined by the circuitry of said state control circuit means, sAid state signals including a central processor switch signal for determining one central processor as being active and corresponding to at least one state change, and further including a storage means switch signal in one of said states for determining one storage means as being primary and being associated with said active central processor corresponding to a desired storage means being coupled with the active central processor, said recovery control circuit means further including means for generating a system recovery signal to initiate said system recovery program when either of said central processor switch signal or said storage means switch signal is generated; maintenance access circuit means responsive to program controlled signals for generating configuration signals representative of a desired configuration of said central processors and storage means; and configuration control circuit means responsive to said central processor switch signal and said storage means switch signal of said recovery control circuit means and responsive to said configuration signals of said maintenance access circuit means, and including a first switching circuit means for controlling the switching of said central processors and second switching circuit means for controlling the coupling of said first and second storage means with said first and second central processors.
 2. The system of claim 1 wherein said state control circuit means of said recovery control circuit means comprises bistable circuit means for defining said states, said states including S0, S1, S2 and S3, and wired logic circuit means for controlling the state of said bistable circuit means wherein said bistable circuit means can switch in response to said error signals from state S0 only to state S1 and from state S1 only to state S2 and from state S2 only to state S3 and from state S3 only to state S2, said bistable circuit means being capable of being reset to state S0 from either of states S1, S2 or S3, said recovery control circuit means generating said central processor switch signal only if the standby central processor is capable of becoming active and whenever said bistable circuit means switches from said state S1 to state S2 or from state S3 to state S2, said recovery control circuit means further generating signals calling for said first storage means becoming primary in said state S2 and for said second storage means becoming primary in said state S3.
 3. The system of claim 2 wherein said recovery control circuit means further comprises circuit means responsive to instruction signals from said system recovery program for switching from state S1 to state S2, from state S2 to state S3, and from state S3 to state S2.
 4. The system of claim 1 further comprising input/output circuit means responsive to said second switching circuit means of said configuration control circuit means for selectively communicating a designated storage means as the primary storage means in a configuration.
 5. The system of claim 4 wherein each of said storage means includes an address bus, a data bus and a return bus, and wherein said input/output circuit means include gating means for selectively communicating each of said buses of said storage means for communication with a selected one of said central processors.
 6. The system of claim 5 wherein said second switching circuit means of said configuration control circuit means comprises a plurality of bistable circuits responsive to instruction signals received from said maintenance access circuit means for selecting predetermined ones of each of said buses of each of said storage means for selective communication with said central processors in accordance with a desired configuration, whereby independent program control over the resulting configuration may be achieved.
 7. A programmable data processing system having first and second central data processors each including processing circuits and maintenance cIrcuits, and first and second storage means provided respectively with first and second bus means for coupling to said data processors, said maintenance circuits sensing conditions within said system to generate error signals upon detection of faults, said system further generating recovery reconfiguration instruction signals under program control, wherein the improvement comprises: sybsystem means in each data processor responsive to said error signals only when its associated data processor is active, for reconfiguring said first and second data processors and said first and second storage means to form new configurations thereof thereby to provide an active data processor and a standby data processor, said subsystem means including recovery control circuit means responsive to said error signals, and including state control circuit means for generating state signals representative of predetermined configuration states defined as S0, S1, S2 and S3, and control circuit means responsive to said error signals, and said state signals to further change the state of said state control circuit and to generate a set storage copy bus signal when said state control circuit is in said S2 state, and a switch processor signal both when said state control circuit is changing from said S1 state to said S2 state or from said S3 state to said S2 state; configuration control circuit means responsive to said recovery reconfiguration instruction signals, the configuration control circuit means in the active central processor being responsive to said switch processor signal only when the standby data processor is capable of becoming active and including a first circuit for controlling the switching of said data processors; and second bus control circuits for generating bus control signals; and input/output circuit means responsive to said bus control signals for connecting the designated storage means bus as the primary store bus coupled to the active central data processor.
 8. The system of claim 7 wherein said configuration control circuit means includes a processor active unit bistable circuit having a first section including first and second input leads and one output lead associated with one of said central processors and a second section having third and fourth input leads and a second output lead associated with the other of said central processors, said first and third input leads being cross-coupled with the other central processor whereby each of said sections may be made active only when the other section is inactive and said second and fourth input leads are responsive to the switch level signals of its associated recovery control circuit means, and wherein said first and second output leads generate signals representative respectively of an active level in one of said central processors.
 9. The apparatus of claim 7 wherein said recovery control circuit means further includes a self-contained timing generator responsive to one of said error signals for generating timing signals to advance the state of said state control circuit means and to control the timing of the generation of said switch processor signal and said switch instruction store signal.
 10. The system of claim 7 wherein said first and second bus means of said first and second storage means each includes an address bus, a data bus and a return bus, and wherein said input/output circuit means includes first gating circuitry for controlling the switching of said address bus, second gating circuitry for independently controlling the switching of said data bus, and third switching circuit means for independently controlling the switching of said return bus.
 11. The system of claim 7 wherein said bus control circuits of said configuration control circuit means further includes a plurality of bistable circuits responsive to said copy bus signal of said recovery control circuit means and to programmed instruction signals for generating signals representative of a desired configuratioN of said storage means communicating with said central processors. 